1. Field of the Invention
The present invention relates to a solid-state imaging device and a camera system.
2. Description of the Related Art
A CMOS (Complimentary Metal Oxide Semiconductor) image sensor (CIS) has a feature that read addresses can be set relatively freely with respect to a CCD (Charge Coupled Device) image sensor.
For example, a sensor having functions of “addition” which reads plural pixel signals at the same time, “thinning-out” which reads pixel signals intermittently while skipping rows and columns, “cut-out” which reads signals only from part of pixels instead of reading all pixels of the sensor is widely used.
“Addition”, “thinning-out” and “cut-out” are occasionally performed at the same time.
As reading and shutter operations are complicated in the sensor having functions of “addition”, “thinning-out” and “cut-out”, a decoder is used for row selection instead of a shift register in many cases.
In the image sensor, a phenomenon called “blooming” is known, in which signal charges flow from a saturated photodiode (hereinafter, referred to as PD) to an adjacent PD and the signal amount varies.
Particularly in the “thinning-out” mode, blooming occurs unless charges accumulated in pixels not to be read are suitably swept out, which reduces image quality.
In response to the above, a method of suppressing blooming by releasing a shutter for sweeping out charges from pixels not to be read (blooming prevention shutter) is proposed (refer to JP-A-2008-193618 (Patent Document 1)).
In this method, plural rows are selected at the same time in the case in which the blooming prevention shutter is released at the time of operating “thinning-out” and in the case of operating “addition”.
FIG. 1 is a view showing an example of addresses of read and shutter rows when two rows are “added” and half of rows is “thinned out”.
At time “t5”, row-addresses “n+9” and “n+11” are selected at the same time and added to be read.
Row addresses “n+17” and “n+19” are shutters for a reading frame, row addresses “n” and “n+2” are shutters for a next frame and row addresses “n+21”, “n+23” and “n+4” and “n+6” are blooming prevention shutters.
In order to select plural rows as the above example, a row selection circuit in which address latches are provided at respective rows is proposed (refer to JP-A-2008-288903 (Patent Document 2)).
FIG. 2 is a diagram showing configurations of a row selection circuit and a row selection timing control circuit.
FIG. 3 is a view showing a timing chart of circuits of FIG. 2.
A circuit 1 of FIG. 2 is configured by including a latch circuit 2 and a row selection circuit 3.
The latch circuit 2 includes two SR latches LTC1, LTC 2 in each row.
The row selection circuit 3 includes 2-input AND gates AG1 to AG5 corresponding to outputs of the SR latches LTC1, LTC 2 of each row and 2-input OR gates OG1, OG2 performing OR operation of them.
In this configuration, the function of selecting arbitrary plural rows is realized by setting only latches of rows to be selected.